I'm attempting to write an assembler for Notch's DCPU-16 spec. The original spec for this CPU can be found here.
The relevant lines:
SET A, 0x30 ;7c01 0030
...
IFN A, 0x10 ;c00d
I understand the instructions up to this point, but this one to me should be at least 2 words long rather than just 0xc00d
SET A, 0x10
would be 7c01 0010. so
IFN A, 0x10
should be 7c0d 0010 shouldn't it?
Why does the b argument in IFN, not cause the instruction to need a [PC++] or nextword component?
0x1f: next word (literal)
0x20-0x3f: literal value 0x00-0x1f (literal)
This is the core part of the spec you are asking about. A literal value between 0 and 31 (0x1f) can be encoded in the opcode. If the value is too large then the literal value needs an extra word, indicated with 0x1f.
So IFN A, 0x10 needs only one word since the 0x10 literal is small enough to fit inside the opcode. The 16-bit opcode breaks down in 6 bits for the b operand, 6 bits for the a operand and 4 bits for the instruction. So b = 0x30 (0x20+literal), a = 0x00 (register A), instr = 0xd (IFN). Put them together with opcode = (b << 10) | (a << 4) | instr; and you get 0xc00d.