All,
I'm trying to modify a Makefile to use a embedded cross compiler instead of the PC's compiler. The Makfile does not have the normal CC or CXX variables. In fact, it appears that is calls another makefile with the variable '@${MAKE}'. How can I override the '@${MAKE}' variable to force the makefile to use a diffent compliler?
Thanks In Advance,
# GNU Make solution makefile autogenerated by Premake
# Type "make help" for usage help
ifndef config
config=debug
endif
export config
PROJECTS := json openjaus
.PHONY: all clean help $(PROJECTS)
all: $(PROJECTS)
json:
@echo "==== Building json ($(config)) ===="
@${MAKE} --no-print-directory -C .build -f json.make
openjaus: json
@echo "==== Building openjaus ($(config)) ===="
@${MAKE} --no-print-directory -C .build -f openjaus.make
I edited the Makefile based on Rob's comments, now I'm receiving the message below, not sure what to do?
make[1]: Nothing to be done for `/home/botbear/openwrt/trunk/staging_dir/toolchain-arm_v6k_gcc-linaro_uClibc-0.9.32_eabi/bin/arm-openwrt-linux-uclibcgnueabi-g++'.
You'd have to look inside json.make and openjaus.make to see how they build programs. If they use the conventional variables, you might be able to do something like:
${MAKE} CC=/usr/bin/gcc-arm CXX=/usr/bin/g++-arm --no-parent-directory ...