I'm trying to parameterize my makefile targets. Currently, it has a
TARGET = main
declaration near the top. It derives the SRC list from that as well as does lots of other things.
I've changed my C code though, so that I have multiple different top level .c files to basically get variant builds. So what I want to be able to do is basically do
make target1
or
make target2
And vary what TARGET is set to in the makefile. I'm confused how to accomplish this. I thought I might add something like
target1: all
TARGET=target1
This didn't seem to work too well at all though. Is there a general pattern for how one does this?
Parameterized variable names and target-specific variables may do what you want, as the value of a target-specific variable is normally "inherited" by the prereqs of that target (assuming you are using GNU make):
target1_SRC=123 456
target2_SRC=abc def
target1: TARGET=target1
target2: TARGET=target2
target1: all
target2: all
all: ; @echo $($(TARGET)_SRC)
Then you can run make target1 or make target2, for example:
$ make target1
123 456
$ make target2
abc def