I wrote a parallel-in serial-out shift register, which I present here.
module shiftreg32b (clk, reset, shift, carrega, in, regout);
input clk;
input reset, shift;
input carrega;
input [31:0] in;
output regout;
reg [31:0] inreg;
assign regout = inreg[31];
always @ (posedge clk)
begin
if (reset == 1) inreg <= 32'd0;
else if (carrega) inreg <= in;
else if (shift) inreg <= {inreg[30:0], 1'b0};
end
endmodule
The problem I found is that the output for this shift register is always an unknown (StX), even when I've set assign regout = 0; to be sure. The test is very simple, and everything else is working fine (inreg shifts when shift is enabled, etc).
Am I using the assign in a wrong way? Can anyone point to the problem?
The assign is correct.
Since you didn't provide a testbench, my best guess is that you have multiple drivers of regout, most likely when you connected the output port up to something else.
Using this minimal testbench, I see regout change from X to 0, as expected
module tb;
reg clk;
reg reset, shift;
reg carrega;
reg [31:0] in;
wire regout;
initial begin
$monitor($time, " regout=%b", regout);
$dumpvars;
clk = 0;
reset = 1;
carrega = 0;
shift =0;
in=0;
#50 $finish;
end
always #5 clk = !clk;
shiftreg32b shiftreg32b (clk, reset, shift, carrega, in, regout);
endmodule
Prints:
0 regout=x
5 regout=0