verilogsystem-verilogtest-bench

What's the best way to tell if a bus contains a single x in Verilog?

I have a test bench that monitors a bus. Some of the signals (bits) within the bus can be 1'bx. For a variety of reasons, I need to know if any of the signals within the bus are 1'bx. What's the best way to test (not for synthesis -- only for simulation purposes) if a bus contains any x's? I had hoped that I could use a reduction OR and then use ===, but this doesn't seem to work.

Solution

  • (^bus === 1'bX)

    Bit-wise xor the bus then check if the result is X. If any bit is X or Z then the result will be X.

    To know which bit in the bus has the error:

    always @* begin
  for(integer i=0; i<$size(bus); i++) begin
     if(bus[i]===1'bX) $display("bus[%0d] is X",bus[i]);
     if(bus[i]===1'bZ) $display("bus[%0d] is Z",bus[i]);
  end
end