verilog

"Invalid Module Instantiation" Error in Mealy sequence detector - Verilog

I have defined a module for a Mealy State Machine that detects a particular sequence. I haven't encoded states as is usually a better choice as I wanted to do it the other way(I saw a similar example in a book, but the code was in VHDL).

module seq_detector(y_out,Clk,x_in);
  output y_out;
  reg y_out;
  input x_in, Clk;
  reg Q1,Q2,Q3,Q4;
  always @(posedge Clk)
    Q1 <= (Q1&&(!Q3))||((!Q1)&&Q2;&&(!Q3)&&(!Q4)&&(x_in));
    Q2 <= ((!Q3)&&Q4;&&(!x_in))||(Q1&&Q2;&&(!Q3)&&(!Q4)&&x_in);
    Q3 <= Q1&&Q2;&&(!Q3)&&(x_in);
    Q4 <= (Q1&&Q2;&&(x_in))||(Q1&&(!Q4)&&(!x_in))||((!Q1)&&(!Q2)&&(Q4)&&(!x_in))||((!Q1)&&(!Q2)&&(x_in))||((!Q1)&&(!Q3)&&Q4;&&x_in)||(Q1&&Q2;&&(!Q4)&&x_in);

  always @(x_in or Q1 or Q2 or Q3 or Q4)
  y_out <= Q3||(Q2&&(!Q4)&&x_in);
endmodule

On compiling the code, I get the following errors. 

mini_project.v:8: syntax error
mini_project.v:8: error: Invalid module instantiation
mini_project.v:9: error: Invalid module instantiation
mini_project.v:10: error: Invalid module instantiation

I can't make out anything of the error message. Can someone please explain the error message and suggest how to correct it ?

Solution

  • You are missing begin and end keywords in your always block. The code thinks that you are trying to instantiate a module rather than do signal assignments. Only the first line will be captured under the always block (the Q1 assignment). The others will not. Try this:

    always @(posedge Clk)
begin
  Q1 <= (Q1&&(!Q3))||((!Q1)&&Q2;&&(!Q3)&&(!Q4)&&(x_in));
  Q2 <= ((!Q3)&&Q4;&&(!x_in))||(Q1&&Q2;&&(!Q3)&&(!Q4)&&x_in);
  Q3 <= Q1&&Q2;&&(!Q3)&&(x_in);
  Q4 <= (Q1&&Q2;&&(x_in))||(Q1&&(!Q4)&&(!x_in))||((!Q1)&&(!Q2)&&(Q4)&&(!x_in))||((!Q1)&&(!Q2)&&(x_in))||((!Q1)&&(!Q3)&&Q4;&&x_in)||(Q1&&Q2;&&(!Q4)&&x_in);
end

    As a side note, this code is really really really ugly. Is there a better way to do this??