SystemVerilog: registering UVM test with the factory

I am confused with the following SystemVerilog construct used for registering the UVM test with the factory:

class random_test extends uvm_test;
    `uvm_component_utils(random_test);
    ...
    function new (...

Here we have a definition of the class random_test, and inside of the definition we call a method whereas its argument is the class that is being defined.

Here are my questions:

1. Is `uvm_component_utils being called at time 0 even before any object was constructed out of random_test class?
2. How can we pass a class to `uvm_component_utils in that class definition?

`uvm_component_utils is not a method, it is a macro which is evaluated at compile time.

You can see what the macro does in the UVM source code. Take a look at src/macros/uvm_object_defines.svh within the UVM distribution.

Your example for class random_test will expand to something like this:

typedef uvm_component_registry #(random_test,"random_test") type_id;
static function type_id get_type();
  return type_id::get();
endfunction
virtual function uvm_object_wrapper get_object_type();
  return type_id::get();
endfunction   const static string type_name = "random_test";
virtual function string get_type_name ();
  return type_name;
endfunction