[SOLVED] Why is a sum statement so bizarrely synthesized?

Why is a sum statement so bizarrely synthesized?

I have 4 buttons on an FPGA dev board so I wrote

function [HEX0] = Bar(KEY)
  n = uint8(sum(KEY, 'native'));
  ...

Unfortunately, HDL Coder turned it into the following chunk of VHDL:

y := '0';

FOR k IN 0 TO 3 LOOP
  y := y OR KEY(k);
END LOOP;

y_0 := '0' & '0' & '0' & '0' & '0' & '0' & '0' & y;

Which I just don't get. Can you help me figure out what's going on here?

Solution

To understand this, you have to understand the matlab sum with logical inputs and native option. The sum of logicals is a logical. Thus sum could be replaced with an or

sum([true,true],'native')

And this is exactly what your Coder puts out. The for-Loop implements the sum (sum(KEY, 'native')), where the coder recognizes that it could be implemented using a OR.

Finally, conversion from logical to uint8 is done padding 7 zero bits.