'Illegal output or inout port' error when trying to simulate counter

I am new to verilog HDL and I have zero experience in digital circuit. I learned one or two things off the internet and now I am trying to write a test bench script for a counter script. I've obtained counter script from following website:

http://www.asic-world.com/verilog/verilog_one_day2.html#Variable_Assignment

Counter:

module counter(clk,rst,enable,count);
input clk, rst, enable;
output [3:0] count;
reg [3:0] count;

always @(posedge clk or posedge rst) begin 
if (rst) begin
    count <= 0;                 
end 
else begin: COUNT           
        while (enable) begin
            count <= count + 1;
            disable COUNT;
        end
end
end
endmodule

Then I have written a testbench as follows:

Test Bench

// counter test bench
`timescale 1ns/100ps
module counter_tb;
    
    reg clk_in;         // using wire won't let value to change inside initial blcok
    reg rst_in;
    reg enable_in;
    reg[3:0] count_out;
    
    counter counter_uut(.clk(clk_in), .rst(rst_in), .enable(enable_in), .count(count_out));
    
    initial begin
    
        // initialize clock, rst and others
        clk_in = 1'b0;          // clock toggles every 5 ns .... see REF_1
        rst_in = 1'b0;          // always NOT reseting
        enable_in = 1'b1;       // always counting
    end
    
    always begin 
        #5 clk_in =~ clk_in;   // ....saw REF_1
    end
    
endmodule

I get error message:

# ** Error: (vsim-3053) C:/Users/Daniel/Desktop/Verilog_Practice/Couter/Counter_tb.v(10): Illegal output or inout port connection for "port 'count'".

I've been struggle for hours trying to resolve the error. Can anyone tell me what is wrong with my testbench?

A reg is only used for procedural assignments to a signal in an always or initial block. For continuous assignments, such as connecting to a module output, use a wire instead. Change:

reg[3:0] count_out;

to:

wire [3:0] count_out;