Why "Procedure Call Standard for the ARM Architecture" (AAPCS) requires SP to be 8-byte aligned?

Since this is a recurring topic, I'm putting up a question about it.

According to AAPCS:

5.2.1.1 Universal stack constraints

• SP mod 4 = 0. The stack must at all times be aligned to a word boundary

5.2.1.2 Stack constraints at a public interface

• SP mod 8 = 0. The stack must be double-word aligned.

What is the rational behind 8-byte alignment?

There are many possible reasons;

1. Tools from require it.
2. ldrd/strd require it on certain architectures.
3. Many ARM buses are 64bit wide. 8byte alignment will result in faster memory access.
4. Caches are also aligned and generally wider than 64 bits (128B, 1024b).
5. Page table and TLBs will straddle sizes larger than 64bits (1k or 4k+).
6. Tagged pointers can be used in exception (C++, signals, etc) frame walking code. The eight byte alignment allows for an additional bit to be used.

The only one that matters, The standard says so. Your compiler and tools will not inter-operate if you do not comply with this. Mainly item 1 will mean that the tools will not inter-operate. The code will fetch the wrong values or a machine exception will be thrown. If exception handling code makes use of item 5, it may also break things.

Mainly, that fact that someone made the choice means that people can take advantage of this fact for what ever use they like and still inter-operate. Compilers will follow the advice of the standard because they need to inter-operate with other libraries and code which may not have been generated by them.

It is also important to note that this applies to ARMv7/A. For example revision 0 of Cortex M3 (CM3_r0) does not align SP to a multiple of 8 on entry to exceptions.

ABI for the ARM® Architecture Advisory Note – SP must be 8 - byte aligned on entry to AAPCS - conforming functions