verilogsystem-veriloghdlsynopsys-vcs

How do I fix "Error-[ICPSD] Invalid combination of drivers"?


I am trying to debug my code shown below. I am fairly new to SystemVerilog and hopefully I can learn from this. Let me know of any suggestions.

**The errors I am receiving are:

  Error-[ICPSD] Invalid combination of drivers
  Variable "Q" is driven by an invalid combination of structural and 
  procedural drivers. Variables driven by a structural driver cannot have any 
  other drivers.
  "divide.v", 13: logic [7:0] Q;
  "divide.v", 16: divide8bit testcase1(x, y, clk, Q, R);
  "divide.v", 23: Q = 8'b0;

  Error-[ICPSD] Invalid combination of drivers
  Variable "R" is driven by an invalid combination of structural and 
  procedural drivers. Variables driven by a structural driver cannot have any 
  other drivers.
  "divide.v", 13: logic [7:0] R;
  "divide.v", 16: divide8bit testcase1(x, y, clk, Q, R);
  "divide.v", 24: R = y;

**My SystemVerilog Code is:

module divide8bit(
  input logic [7:0] x,y,
  input logic clk,
  output logic [7:0] Q,R);

  always_ff @(posedge clk)
    begin
      R <= R-x;
      Q <= Q + 8'd1;
    end
endmodule

module test1;

  logic [7:0] x,y,Q,R;
  logic clk;

  divide8bit testcase1 (x,y,clk,Q,R);

  initial 
    begin
            x = 8'd2;
            y = 8'd8;
            Q = 8'd0;
            R = y;
            clk = 1'd0;
            while(x <= R)
                begin
                    #5 clk = ~clk;
                end
            #5 $finish; 
        end
endmodule

Solution

  • Same problem here: you are assigning to Q and R inside module test1. At the same time module testcase1 is also trying to assing to Q and R. Don't assign to Q and R in test1!