filetextoutputvhdltextwriter

Text output file not instantiated


I have two newbie questions. I am attempting to output the data from an array into a text file on vhdl. Despite referencing many online guides to do this, I always come up with a "file does not exist". Any suggestions on what's going wrong?

Secondly, when I try to use the array signal below as an argument to the write function, it gives an error. How else can I use non-constant data as an operand?

entity Top_Module is
Port ( clk : in  STD_LOGIC);
end Top_Module;

architecture Behavioral of Top_Module is

type array_1 is array (0 to 127) of integer range -128 to 127;
signal sample_1: array_1  := (104,40,-40,-104,-128,-104,-40,40,104,127,104,40,40,-4);
constant  a :std_logic_vector(3 downto 0):= "0111";
begin


process(clk)    -- process for writing the outputs to the "*.txt" file
file result_file: text  is out "fft_output.txt";
variable outline:line;
constant tmp_fft:integer:=0;
begin
    if(clk'event and clk='1') then
                --tmp_fft  :=to_integer(signed(sample_1));
                write(outline,a);
                writeline(result_file,outline);
    end if;
end process;

Solution

  • The file declaration is VHDL 1987 syntax, so try with this instead:

    file result_file : text open write_mode is "fft_output.txt";
    

    Your code does not show it, but I assume you include the std.textio package like:

    library std;
    use std.textio.all;
    

    In VHDL 2002, this package does not know how to make (write) a line from std_logic_vector as attempted in write(outline, a). So if you are using VHDL 2002, the problem may be due to lacing support for std_logic_vector arguments in the write procedure.

    The non-standard Synopsys package std_logic_textio is available in most tools, and includes a write function for std_logic_vector. This package can be used with:

    library ieee;
    use ieee.std_logic_textio.all;
    

    VHDL 2008 standard added support for write of std_logic_vector in the std_logic_1164 package, so you may want to check if the simulator you are using has support for this feature in VHDL 2008. Note that binary and hex output is also supported with bwrite and hwrite.

    Note that synthesis using write and in general textio is not possible, since these are based on the line type, which again is an access type, similar to pointer types in other languages, and this can't be synthesized. For synthesis use a function the the slv_image in David Koontz's answer.