I am trying to display digital circuit netlist with graphviz.
I am resorting to :
The following code works fine. However, during layout, some inputs (here "i3") can be misaligned : I would expect i3 to be left-aligned, as for i1 and i2.
How can I do that ?
digraph G {
graph [rankdir = LR];
node[shape=record];
c1[ label="{ {<i1>i1|<i2>i2}| c1 | {<f>f} }"];
c2[ label="{ {<i0>i0}| c2 | {<out_0>out_0} }"];
c3[ label="{ {<i0>i0}| c3 | {<out_0>out_0} }"];
c4[ label="{ {<i0>i0|<i1>i1}| c4 | {<out_0>out_0} }"];
i1; i2; i3; f; i1 -> c2:i0[ label="w(1)"];
i2 -> c3:i0[ label="w(2)"];
i3 -> c4:i1[ label="w(4)"];
c1:f -> c4:i0[label="w(3)"];
c2:out_0 -> c1:i1[label="w(5)"];
c3:out_0 -> c1:i2[label="w(6)"];
c4:out_0 -> f[label="w(7)"];
}
Just specify that i1, i2 and i3 share the same rank:
digraph G {
graph [rankdir = LR];
node[shape=record];
c1[ label="{ {<i1>i1|<i2>i2}| c1 | {<f>f} }"];
c2[ label="{ {<i0>i0}| c2 | {<out_0>out_0} }"];
c3[ label="{ {<i0>i0}| c3 | {<out_0>out_0} }"];
c4[ label="{ {<i0>i0|<i1>i1}| c4 | {<out_0>out_0} }"];
i1; i2; i3; f; i1 -> c2:i0[ label="w(1)"];
i2 -> c3:i0[ label="w(2)"];
i3 -> c4:i1[ label="w(4)"];
c1:f -> c4:i0[label="w(3)"];
c2:out_0 -> c1:i1[label="w(5)"];
c3:out_0 -> c1:i2[label="w(6)"];
c4:out_0 -> f[label="w(7)"];
{rank=same; i1; i2; i3}
}