My assignment is to code a simple 2 to 4 decoder and then display the possible outcomes and waveform.
I am using the gEDA suite along with Icarus Verilog (iVerilog) as a compiler and GTKWave for the waveform.
This is my first time coding with Verilog or working with the gEDA suite. From googling it appears I need to follow this designflow:
The testbench file wont compile and I am not sure why, I have tried several variations and I keep getting errors. Any help is much appreciated. Thank you.
Here is my design file code:
// 2 to 4 Decoder
// File Name: decoder.v
module decoder(X,Y,E,Z);
input X,Y,E;
output [0:3]Z;
wire [0:3]Z;
wire X1, Y1;
not
inv1(X1,X),
inv2(Y1,Y);
and
and1(Z[0],X1,Y1,E),
and2(Z[1],Y1,X,E),
and3(Z[2],Y,X1,E),
and4(Z[3],X,Y,E);
endmodule
Here is my testbench code:
module decoder_tb;
input X,Y,E;
output [0:3]Z;
//wire [0:3]Z;
//wire X1, Y1;
// should create .vcd dump file for GTKWave
initial
begin
$dumpfile("decoder.vcd");
$dumpvars();
end
decoder decode(X,Y,E,Z);
initial
begin
$display($time,"<< Z[0]=%d Z[1]=%d Z[2]=%d Z[3]=%d >>", Z[0] , Z[1] , Z[2] , Z[3] );
end
initial
begin
#0
X = 0; Y = 0; E = 1;
#5
X = 0; Y = 1; E = 1;
#10
X = 1; Y = 0; E = 1;
#15
X = 1; Y = 1; E = 1;
end
endmodule
The commands in terminal I am using are:
iverilog -o decoder.vvp decoder.v decoder_tb.v
gtkwave decoder.vcd
EDIT: Here is the exact error message
aj@aj:~/verilogCode$ iverilog -o decoder.vvp decoder.v decoder_tb.v
decoder_tb.v:26: error: X is not a valid l-value in decoder_tb.
decoder_tb.v:6: : X is declared here as wire.
decoder_tb.v:26: error: Y is not a valid l-value in decoder_tb.
decoder_tb.v:6: : Y is declared here as wire.
decoder_tb.v:26: error: E is not a valid l-value in decoder_tb.
decoder_tb.v:6: : E is declared here as wire.
decoder_tb.v:28: error: X is not a valid l-value in decoder_tb.
decoder_tb.v:6: : X is declared here as wire.
decoder_tb.v:28: error: Y is not a valid l-value in decoder_tb.
decoder_tb.v:6: : Y is declared here as wire.
decoder_tb.v:28: error: E is not a valid l-value in decoder_tb.
decoder_tb.v:6: : E is declared here as wire.
decoder_tb.v:30: error: X is not a valid l-value in decoder_tb.
decoder_tb.v:6: : X is declared here as wire.
decoder_tb.v:30: error: Y is not a valid l-value in decoder_tb.
decoder_tb.v:6: : Y is declared here as wire.
decoder_tb.v:30: error: E is not a valid l-value in decoder_tb.
decoder_tb.v:6: : E is declared here as wire.
decoder_tb.v:32: error: X is not a valid l-value in decoder_tb.
decoder_tb.v:6: : X is declared here as wire.
decoder_tb.v:32: error: Y is not a valid l-value in decoder_tb.
decoder_tb.v:6: : Y is declared here as wire.
decoder_tb.v:32: error: E is not a valid l-value in decoder_tb.
decoder_tb.v:6: : E is declared here as wire.
12 error(s) during elaboration.
In your testbench, change input
to reg
and output
to wire
. This fixes the compile errors for me (although, I am not using gEDA or iVerilog):
module decoder_tb;
reg X,Y,E;
wire [0:3]Z;
My simulators gave much more meaningful error messages than yours in this case:
Identifier 'X' does not appear in port list.