[SOLVED] Case statements in Verilog?

Case statements in Verilog?

Say I have a 8 bit output reg called "myReg" and a 8 bit input called "checkReg". Can I check and assign their values in a case statement using hex values?

For instance (assume the code is in an always block)

case (checkReg)
    2'hA0:myReg <= 2'h10;
    2'hB0:myReg <= 2'hC0;
    //Other cases
endcase

I want the above piece of code to do the following: If checkReg = 10100000, set myReg to 00010000. If checkReg = 10110000, set myReg to 11000000.

I wasn't sure if I could check and assign hex values to a vector and have it automatically converted to binary.

Solution

For straight base conversion (bin,oct,hex,dec) you do not need to do any special conversion in verilog. Things like BCD conversion does requires extra steps.

The number before the single-quote is the bit size, not the digit count. 2'hA0 should be 8'hA0, else the upper bit values will be masked.

reg [7:0] myReg;
always @* begin
  case (checkReg)
    8'hA0: myReg = 8'h10;
    8'hB0: myReg = 8'hC0;
    //Other cases
  endcase
end