Why am I getting parse error in reg declaration?

I'm getting a parse error from line 15 of this code:

12: module DoShellSort(
13:    input [10*20-1:0] toSort,
14:    output [10*20-1:0] sorted
15:    reg arrBitSize
16: );

Here's the part of my testbench where I'm initializing the input and reg variables:

module ShellSort_tb;
    reg [10*19:0] toSort, arrBitSize;
    wire [10*19:0] sorted;
    integer i;
    
    DoShellSort ss_tb ([10*19:0] toSort, [10*19:0] sorted, arrBitSize);
    
    // Input values you want to sort here
    // Note: Should be 20 bits in size
    initial $readmemh ("memory_hex.txt", toSort);

    initial begin
        #1 $display("\nThis program implements SHELL SORT to arrange values.\n");
        
        // Display initial array
        #10 $display("Array to sort: ");
        #10 for (i = 0; i < arrBitSize + 1; i = i + 1)
            $write("%h", toSort[i]);
            
        #10 arrBitSize = 4'd9;
        
        // ................
endmodule

I'm synthesizing using iverilog. Here is the error message:

Why am I getting a parse error?

There is an error with the way you have defined your ports, you are missing a comma and port direction or have put rweg in the wrong place and missing a comma. You have:

 module DoShellSort(
    input [10*20-1:0] toSort,
    output [10*20-1:0] sorted //missing comma?
    reg arrBitSize            //missing port direction?
);

I think you meant this:

 module DoShellSort(
    input      [10*20-1:0] toSort,
    output reg [10*20-1:0] sorted, arrBitSize
);

I find it better practice to list each port separatly, as this make it easier to update code and the interface is clear even to those not as familiar with the language.

 module DoShellSort(
    input      [10*20-1:0] toSort,
    output reg [10*20-1:0] sorted, 
    output reg [10*20-1:0] arrBitSize
);