Why is this Shift Register not loading properly in VHDL?

I have a custom designed shift register that has as input DL(leftmost input), DR(rightmost), CLR that clears and loads DR, S that shifts right and W that loads leftmost. After testing it, the rightmost is being loaded but not the left. I have reread the code multiple times, but I can't figure out what is wrong. Here's the code:

    library IEEE;
use IEEE.std_logic_1164.all;

entity shiftregister is
    port (
        CLK, CLR: in STD_LOGIC;
        S: in STD_LOGIC; --Shift right
 W: in STD_LOGIC; --Write
 Cin: in STD_LOGIC; --possible carry in from the addition
        DL: in STD_LOGIC_VECTOR (7 downto 0); --left load for addition result
 DR: in STD_LOGIC_VECTOR (7 downto 0); --right load for initial multiplier
        Q: out STD_LOGIC_VECTOR (15 downto 0)
     );
end shiftregister ;

architecture shiftregister of shiftregister is
signal IQ: std_logic_vector(15 downto 0):= (others => '0');
begin
   process (CLK)
   begin
 if(CLK'event and CLK='1') then 
          if CLR = '1' then 
   IQ(7 downto 0)  <= DR;  --CLR clears and initializes the multiplier
   IQ(15 downto 8) <= (others => '0');
   else 
  if (S='1') then
    IQ <= Cin & IQ(15 downto 1);
  elsif (W='1') then
    IQ(15 downto 8) <= DL;
  end if;
          end if;

 end if;  
    end process;
Q<=IQ;
end shiftregister;

Waveform

TestBench

library IEEE;
use IEEE.std_logic_1164.all;

entity register_tb is
end register_tb;

architecture register_tb of register_tb is
    component shiftregister is port (
        CLK, CLR: in STD_LOGIC;
        S: in STD_LOGIC; --Shift right
        W: in STD_LOGIC; --Write
        Cin: in STD_LOGIC; --possible carry in from the addition
        DL: in STD_LOGIC_VECTOR (7 downto 0); --left load for addition result
        DR: in STD_LOGIC_VECTOR (7 downto 0); --right load for initial multiplier
        Q: out STD_LOGIC_VECTOR (15 downto 0)
    );
    end component;

    signal CLK: std_logic:='0';
    signal CLR: std_logic:='1';
    signal Cin: std_logic:='0';
    signal S: std_logic:='1';
    signal W: std_logic:='0';
    signal DL, DR: std_logic_vector(7 downto 0):="00000000";
    signal Q: std_logic_vector(15 downto 0):="0000000000000000";
begin 
    U0: shiftregister port map (CLK, CLR, S, W, Cin, DL,DR,Q);

    CLR <= not CLR    after 20 ns;
    CLK <= not CLK    after 5 ns;
    W   <= not W      after 10 ns;
    DL  <= "10101010" after 10 ns;
    DR  <= "00110011" after 10 ns;

end register_tb;

Your simulation shows that your S input is always high. The way you have your conditions setup, this means that the last elsif statement will not execute because S has priority over W. If you want your write to have priority over your shift operation, you should switch your conditions

if (W='1') then
  IQ(15 downto 8) <= DL;
elsif (S='1') then
  IQ <= Cin & IQ(15 downto 1);
end if;

Based on your comment for the desired behaviour, you could do something like this:

if (S='1' and W='1') then
  IQ  <= Cin & DL & IQ(7 downto 1);
elsif (W='1') then -- S=0
  IQ(15 downto 8) <= DL;
elsif (S='1') then -- W=0
  IQ <= Cin & IQ(15 downto 1);
end if; -- W=0 & S=0