I am using the iverilog
simulator, and I want to pass value to N
during compilation. Which command do I need to use, and can anyone help me with the usage of `define
?
`define N
module Nbcd(A, B ,S);
input [N*4-1:0] A,B;
output[N*4-1:0] S;
genvar i;
generate
for(i=0; i<=N-1; i=i+1)
bcd (.A(A[4*i+3:i*4]),
.B(B[4*i+3:i*4]).
.S(S[4*i+3:i*4])
);
endgenerate
endmodule
Testbench
module Nbcd();
reg [N*4-1:0] A,B;
wire [N*4-1:0] S;
integer i;
Nbcd U1 (.A(A),.B(B),.S(S));
initial begin
for (i=o; i<=N-1; i=i+1)
begin
A=i;
b=i+1;
end
endmodule
I believe that most simulators allow the -define
command line option.
irun test.sv -define N=0
It is slightly different for iverilog use -Dkey=value
ie
-DN=0
To use `define
(tick defines) you need to place a tick before it, so you use `N
when you want to use the command line supplied value, eg:
module Nbcd(A, B ,S);
input [`N*4-1:0] A,B;
output[`N*4-1:0] S;
I have a working example on EDA Playground, with iverilog version 0.9.7. The value is supplied via command line -DN=10
and displays this value in the simulation using $display("N : %d", `N);
.
You may also want to add the code below, so that it can run without the command line option or remind users it is required:
`ifndef N
`define N 0
`endif