toolchainriscvrisc

Setup RISC-V toolchain with specific instruction set

I'm developing a processor using a form of the RISC-V ISA and i'm currently trying to setup the toolchain. My current processor design uses the RV32I base instruction set and i want to compile for this ISA. However the default configuration of the toolchain, as written on the http://RISCV.org site, is to compile for the RV64I ISA.

How can i reconfigure this toolchain to produce a binary for the RV32I ISA?

Solution

  • If you are using the RISC-V port of gcc, you can use the -march flag to constrain which instruction sets and extensions it will emit.

    Example:

    riscv64-unknown-elf-gcc -march=RV32I etc.

    The fact that the compiler name begins with riscv64 is irrelevant. x86 is the same way (the x86 64bit compiler can generate 32-bit ia32 code via "-m32").