The code below shows a finite state machine that controls a separate datapath module to find the GCD of two 4-bit numbers. I am currently getting the following errors, and I'm not sure why. Maybe they are due to some syntax I'm not aware of:
ERROR:HDLCompiler:806 - "D:/Xilinx Stuff/GCD123/Controller.v" Line 48: Syntax error near ";".
ERROR:HDLCompiler:806 - "D:/Xilinx Stuff/GCD123/Controller.v" Line 59: Syntax error near ";".
ERROR:HDLCompiler:806 - "D:/Xilinx Stuff/GCD123/Controller.v" Line 62: Syntax error near ";".
The code where the errors are encountered is below:
module Controller(start,reset,x_sel,y_sel,xlty,xgty,xequaly,clk);
input start,clk, reset, xlty, xgty,xequaly;
output x_sel,y_sel;
// Declare state register
reg [1:0]state;
// Declare states
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4;
debounce startd(.clock(clk),.noisy(start),.clean(clean_start));
always @ (posedge clk or posedge reset) begin
if (reset)
state <= S0;
else
case (state)
S0:
if (clean_start)
state <= S1;
else
state <= S0;
S1:
x_sel <= 0;
y_sel <= 0;
state <= S2;
S2:
if (xlty)
state <= S3;
else if(xgty)
state <= S4;
else if(xequaly)
state <= S5;
S3:
y_sel <= 1;
state <= S2;
S4:
x_sel <= 1;
state <= S2;
S5:
state <= S0;
endcase
end
endmodule
The lines that have the errors are y_sel <= 0;
in the S1
state, state <= S2;
in the S4
state and state <= S2;
in the S3
state.
You need begin/end
keywords around consecutive statements:
module Controller(start,reset,x_sel,y_sel,xlty,xgty,xequaly,clk);
input start,clk, reset, xlty, xgty,xequaly;
output x_sel,y_sel;
// Declare state register
reg [1:0]state;
// Declare states
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4;
debounce startd(.clock(clk),.noisy(start),.clean(clean_start));
always @ (posedge clk or posedge reset) begin
if (reset)
state <= S0;
else
case (state)
S0:
if (clean_start)
state <= S1;
else
state <= S0;
S1:
begin
x_sel <= 0;
y_sel <= 0;
state <= S2;
end
S2:
if (xlty)
state <= S3;
else if(xgty)
state <= S4;
else if(xequaly)
state <= S5;
S3:
begin
y_sel <= 1;
state <= S2;
end
S4:
begin
x_sel <= 1;
state <= S2;
end
S5:
state <= S0;
endcase
end
endmodule