I don't know why it's showing error although syntax seems to be right.
I'm trying to program sramctl where address adds_in is input address and sram_adds output address I am just mapping the address and have not consider the data bus.
library IEEE;
use IEEE.std_logic_1164.all;
entity sramctrl is
port(clk,adsn,blastn,lwdrn,lhold:in std_logic;
adds_in :in std_logic_vector(9 downto 2);
adds_4msb:in std_logic_vector(31 downto 28);
readyn,btermn,sramcsn,sramoen,lholda :out std_logic;
sram_adds:out std_logic_vector(9 downto 2));
end sramctrl;
architecture behavioral of sramctrl is
type state_type is(s0,s1,s2);
signal state:state_type;
begin
process(clk,adsn,blastn,lwdrn,lhold,adds_in,adds_4msb)
begin
variable sa:std_logic:='0';
variable a31_a28 :std_logic_vector(3 downto 0):="0000";
variable temp:std_logic_vector(9 downto 2):="00000000";
if(rising_edge(clk))then
if ((not adsn) and (adds_4msb="0000"))then
a31_28 := adds_4msb;
end if;
if (lhold='1')then
lholda<='1';
else
lholda<='0';
end if;
sa:=lhold and lholda ;
case state is
when s0=>sramoen<='1';
sramcsn<='1';
readyn<='1';
btermn<='1';
if((not adsn) and (not adds_4msb) and sa)then
temp:=adds_in;
if(lwdrn='1')then
state<=s1;
ready<='0';
else
state<=s2;
end if;
else
state<=s0;
end if;
when s1=>sramoen<='1';
sramcsn<='0';
if(lwdrn and (not blastn) and sa)then
sram_adds<=temp;
readyn<='1';
btermn<='1';
state<=s0;
elsif(lwdrn and blastn and sa)then
if(temp=X"fe")then
sram_adds<=temp;
temp:=temp+1;
btermn<='0';
readyn<='0';
state<=s1;
elsif(temp=X"ff")then
sram_adds<=temp;
btermn<='1';
readyn<='1';
state<=s0;
else
sram_adds<=temp;
temp:=temp+1;
btermn<='1';
readyn<='0';
state<=s1;
end if;
else
state<=s2;
end if;
when s2=>sramoen<='0';
sramcsn<='0';
if((not lwdrn) and (not blastn) and sa)then
sram_adds<=temp;
readyn<='1';
btermn<='1';
state<=s0;
elsif((not lwdrn) and blastn and sa)then
if(temp=X"fe")then
sram_adds<=temp;
temp:=temp+1;
btermn<='0';
readyn<='0';
state<=s2;
elsif(temp=X"ff")then
sram_adds<=temp;
btermn<='1';
readyn<='1';
state<=s0;
else
sram_adds<=temp;
temp:=temp+1;
btermn<='1';
readyn<='0';
state<=s2;
end if;
else
state<=s2;
end if;
when others =>state<=s0;
end case;
end if;
end process;
end behavioral ;
I couldn't find a solution. Errors it has popped:
COMP96 Compile Architecture "behavioral" of Entity "sramctrl"
COMP96 ERROR COMP96_0019: "Keyword 'end' expected." "design.vhd" 18 9
COMP96 ERROR COMP96_0019: "Keyword 'end' expected." "design.vhd" 19 3
COMP96 ERROR COMP96_0016: "Design unit declaration expected." "design.vhd"
No your syntax isn't correct.
As noted by Amir :
process(clk,adsn,blastn,lwdrn,lhold,adds_in,adds_4msb)
begin
variable sa:std_logic:='0';
variable a31_a28 :std_logic_vector(3 downto 0):="0000";
variable temp:std_logic_vector(9 downto 2):="00000000";
Should be:
process(clk,adsn,blastn,lwdrn,lhold,adds_in,adds_4msb)
variable sa:std_logic:='0';
variable a31_a28 :std_logic_vector(3 downto 0):="0000";
variable temp:std_logic_vector(9 downto 2):="00000000";
begin
begin separates the process declarative part from the process statement part here.
Also, here:
if ((not adsn) and (adds_4msb="0000"))then
There isn't an and operator that ANDs a std_logic and a boolean (result of the right expression).not is not a logical reduction operator, it returns a std_logic in this case.
should be along the lines of:
if adsn = '0' and adds_4msb = "0000" then
Which ANDs two boolean results. Notice the corrected spelling of adds_4msb.
The next line:
a31_28 := adds_4msb;
has a misspelling, that should be a31_a28.
And here::
if lhold = '1' then
lholda <= '1';
else
lholda <= '0';
end if;
sa := lhold and lholda ;
lholda is an output and in some tools not IEEE Std 1076-2008 compliant can not be read. It also produces a sa that's simply delayed by one delta simulation cycle (no time advancing) and has no meaning other that to trim a delta cycle off the end of holda for sa or off the beginning of lhold. If you're counting on that delta cycle hold over not being there you have a defective design. Delta cycles emulate parallelism and variables shouldn't be counted on for timing relationships. This would imply you don't have a synthesis eligible model of sram_ctl. Synthesis would see lhold and lholda as one and the same, and sa as a different name for the same thing.
Here:
ready<='0';
There is no signal ready present in your design.
And:
if(lwdrn and (not blastn) and sa)then
as well as:
elsif(lwdrn and blastn and sa)then
You're trying to produce a boolean condition with logic operators. (All those parentheses are also redundant) try conditional testing the two expressions to a std_logic value.
These two conditions show up two places each.
And:
temp:=temp+1;
There is no adding operator "+" directly visible (two places). You should either be using package std_logic_unsigned or temp should be an unsigned and you should be using package numeric_std (requiring a type conversion when assigning to sram_adds).