[SOLVED] How to simulate the RISCV Rocket chip

How to simulate the RISCV Rocket chip

According to the riscv-gcc compiler we are generated the binary file. This binary file data are feeding to rocket chip through this signals. io_host_in_valid, input [15:0] io_host_in_bits

Here io_host_in_bits is 16-bit, so we are driving the 2-times for each instruction data in little-Endian mode. We are not getting any response from Rocket core (HTIF). How to simulate the Rocket core and if it is possible to simulate in Xilinx Vivado 2014 as well as debug the design. Can any one help me about this

Regards, Santhosh Kumar.

Solution

For more information on the Rocket Chip infrastructure, I recommend checking out the slides and videos from the first RISC-V Bootcamp.

The Rocket Chip can be simulated/debugged in two different ways: C simulator and Verilog. For information on using these modes, please consult the Rocket Chip README.