4-bit Shift register with flip flop

I want to build a 4-bit shift register using D FlipFlop , but I don't understand this diagram.

This code is given to me for shift register

ENTITY shift4 IS
 PORT ( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; 
 Enable : IN STD_LOGIC;
 Sin : IN STD_LOGIC;
 Clock : IN STD_LOGIC;
 Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; 
END shift4 ; 

And I wrote this code for flip flop

entity flipflop is
 port ( D_in : in std_logic;
 CLK : in std_logic;
 CLR : in std_logic;
 Q_out : out std_logic
 );
end flipflop; 


architecture behavior of flipflop is
begin
process(CLK)
begin
if CLR='0' then null;
elsif RISING_EDGE(CLK) then
Q_out <= D_in;
end if;
end process ;
end behavior ;

What I don't get from this diagram is how am I supposed to use D and how to port map flipflop with this inputs and outputs. I tried this

FF1: flipflop port map(Sin,Clock,Enable, Q(3));
FF2: flipflop port map(Sin,Clock,Enable, Q(2));
FF3: flipflop port map(Sin,Clock,Enable, Q(1));
FF4: flipflop port map(Sin,Clock,Enable, Q(0));

But obviously it's not the case because I have to use the D also, but I can't find a way for using all the variables.

FF1: flipflop port map(Sin,Clock,Enable, Q(3));

This is good, it does exactly what your diagram ask.

FF2: flipflop port map(Sin,Clock,Enable, Q(2));

This is not good. This connects the input D of FF2 to Sin, while the diagram connects it to Q(3). You could try doing something like:

FF2: flipflop port map(Q(3),Clock,Enable, Q(2));

But unless your tool is compatible uses VHDL-2008, it will fail (safer to assume it doesn't). This is because in VHDL you can't read an output of your entity. Instead, you have to define an internal signal, use it for all assignments, and assign Q to it.

architecture structural of shift4 is
    signal Q_i : std_logic_vector(3 downto 0); -- _i stands for internal
begin
    Q <= Q_i; -- Drive output port from the internal version

    FF1: flipflop(Sin, Clock, Enable, Q_i(3));