x86_64, intel core 2 duo.
I searched through the 3 intel doc volumes, and may have missed the right section, hence the question.
A tlb can have up to 4096 entries, that is a lot in my book. But that is not that much in a SMP system after all. Especially if the tlb is not flushed thanks to the tag bit -> almost full all the time.
Imagine the case in which you have your memory properly mapped throughout the 4 page tables. Imagine that you have more than 4096 entries (i know..), and that, obviously, it is too much for the tlb.
I know that x86 doesn't automatically generate page fault on tlb miss.
Should I be assured that the mmu will walk the page tables and replace one of the entries automatically (since it is already correctly mapped) ?
It would make sense, since there is nothing more to do on the operating system side, the memory is already mapped.
Thanks
Yes, on a TLB miss the MMU will walk the page table and replace an existing TLB entry if there is no empty space available to hold the new entry.
A TLB miss will only result in a page fault if the page is not present in memory.