riscvrocket

Include/Exclude L2 from RISC-V Rocket

How do I include/remove the L2 cache in the RISC-V Rocket chip? Is it something I need to change in the rocket chip's config file?

Solution

  • Yes, but you do not need to change the file, just which CONFIG you use. Within Config.scala you can see all of the configs, including the configs leveraging WithL2Cache. For example, say you wanted to use the DefaultL2Config. Whenever you perform a make command within rocket-chip, have CONFIG=DefaultL2Config. You can do this via an export:

    $ export CONFIG=DefaultL2Config

    or on each line

    $ make CONFIG=DefaultL2Config