I am working on TI Jacinto6(ARM CortexA15) based board. I am understanding U-boot source. As per start.S file, following assembly instructions are executed to disable L1 I/D cache and TLB. This instructions are from start.s(http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/start.S;h=fedd7c8f7e00d0427405173849e6c0743d6b886f;hb=524123a70761110c5cf3ccc5f52f6d4da071b959)
mov r0, #0 @ set up for MCR
mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
mcr p15, 0, r0, c7, c10, 4 @ DSB
mcr p15, 0, r0, c7, c5, 4 @ ISB
As per ARM documents CortexA15 is having 4 cores. The above code will disable the cache and TLB on the core which it is running, then what about the other cores cache and TLB. Will the U-boot source runs on only one core? If so then how other cores will be disabled?
Will the U-boot source runs on only one core?
The U-Boot binary (not the source) executes on only one processor core.
The functionality of a bootloader does not require parallel processing.
Also the Linux kernel expects only one core to be enabled when it starts.
If so then how other cores will be disabled?
Typically after a processor/system reset, only one core is enabled; everything else is quiescent or disabled.
So Kernel will enable the other cores while booting?
The OS, assuming it supports SMP (symmetric multiprocessors), will enable the other cores as part of its initialization.
can you please share the kernel source link(git) which enables the other cores.
For an ARM Cortex-A9 quad-core (an A15 would be similar) the Linux kernel outputs:
Booting Linux on physical CPU 0x0
Linux version 3.10.60+wandboard_1.0.2+1.0.0-wandboard (root@host) (gcc version 4.8.3 (crosstool-NG 1.19.0) ) #7 SMP Mon Dec 29 18:49:06 PST 2014
CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c53c7d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: Freescale i.MX6 Quad/DualLite (Device Tree), model: Wandboard Quad based on Freescale i.MX6 Quad
...
L310 cache controller enabled
l2x0: 16 ways, CACHE_ID 0x410000c7, AUX_CTRL 0x32070000, Cache size: 1048576 B
...
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x804bdd30 - 0x804bdd88
CPU1: Booted secondary processor
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
CPU2: Booted secondary processor
CPU2: thread -1, cpu 2, socket 0, mpidr 80000002
CPU3: Booted secondary processor
CPU3: thread -1, cpu 3, socket 0, mpidr 80000003
Brought up 4 CPUs
SMP: Total of 4 processors activated (6324.22 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
...
The Linux kernel begins execution of its C code in start_kernel() in init/main.c.
The second procedure called is the ARM version of smp_setup_processor_id(), which is responsible for the Booting Linux on physical CPU ... message text.
Towards the end of start_kernel(), the ARM version of check_bugs() will invoke check_writebuffer_bugs(), which is responsible for the CPU: Testing write buffer coherency: ... message text.
At the end of start_kernel(), rest_init() eventually initializes the other processor cores through the ARM version of secondary_start_kernel() (CPUn: Booted secondary processor), invoked somehow through smp_init() (Brought up N CPUs).