pythonverilogfpgaiverilogcocotb

Verilog with cocotb : assign statement

My Verilog code is an adder that just uses assign sum = a+b. The problem is that, while running it using cocotb, sum remains unknown, though a and b have valid values.

When I make sum a reg type, it works.

`timescale 1 ns / 1 ps

module adder(input [7:0] a,
        input [7:0] b,
        output reg  [7:0] sum,
        output [7:0] sum2);

    assign sum2=a+b;        // Trouble is here
    always@(a,b) begin
        sum=a+b;            // This works
    end

`ifdef COCOTB_SIM
    initial begin
        $dumpfile("adder.vcd");
        $dumpvars();
    end
`endif
endmodule

gtkwave output

Solution

  • I believe this is actually caused by a bug in Icarus present in v0.9.7.

    If you upgrade to the latest development version you'll find that a continuous assignment works fine. Other simulators also handle the continuous assignment fine.

    If you're stuck on that version of Icarus you can workaround it by putting the assignment inside a process, as you discovered.