compiler-constructionprocessormicroprocessorsriscv

What is meant by the FENCE instruction in the RISC-V instruction set?

While going through the RISC-V ISA, I have seen an instruction in the memory model section (FENCE instruction). What does it mean exactly?

Solution

  • I've found one case when using FENCE instruction is just necessary. Example:

    1. Some module in a SoC generates interrupt by writting value into CSR 0x783 (MIPI) via HostIO bus.
    2. Firmware jumps to the interrupt handler.
    3. Handler tries to reset 'pending' bit in a user implemented device by writting 1 into register.
    4. Such operation was compiled as a 'store' instruction with immediate value =1.
    5. As result, if I don't implement FENCE at the beginning of the handler I have some garbage value instead of proper immediate argument of the instruction.