Designing a System Timer(Porgrammable Logic Timer)

System timer

Computers contain a timer containing programmable channels. Programmable channels mean timers of different durations. How to design such a circuit with four programmable channels, each disabled initially. An enable input, two channel select inputs and 4 lines for duration input can set any channel to a given duration from 1- 15. Zero means to disable a channel. Four output lines correspond to the channels and are set high as soon as the corresponding timer expires.

Inputs Clock Pulse CP

Input Available IA

Channel Select CS0, CS1

Duration D0…D3

Outputs

Timer Expire : TA, TB, TC, TD

I want to use Discrete logic ICs like Flip-Flops,Logic Gates,Decoders,Multiplexers,Encoders, etc.Data input is to be done using buttons(Push-buttons) and output should be displayed on LEDs. The clock should be common.

Single shot Timer consists of:

1. n-bit binary counter

   driven by the input clock source CP and reseted by start input. With each clock pulse increments its value. The reset input should be hooked up to the timer start signal.

2. n-bit LATCH register

   to store the timer Interval value (your per channel duration D0..D3)

3. n-bit comparator

   to compare counted value and the Interval value. The XOR of equal bits is zero so if you or all xored bits together the result is 0 if both LATCH register value and Counter value are the same.

4. output flip flop

   to remember expiration of timer (for non pulse mode operation) the output is your TA.TB,TC,TD The start impulse should also reset the RS on circuit I do this by WR but I suspect you will have Start signal separately instead...

Something like this:

You need to take into account the negations and auxiliary inputs of used ICs to make it work properly (some has negated WR some not ... the same goes for all pins so always check datasheet). So do not forget to add the chip selects and output enables signals to their working conditions.

multi channel timer

Well you just add the LATCH and comparators for each channel each connected to the same counter. The tricky part is the channel selection and starting part. you need to add decoder 1 from 4 to select the correct LATCH while setting the D0..D3. To draw a circuit for that part I would need to know more about the purpose of this ... Also if you set the Intervals only manually then you can use DIP switches instead the LATCH and the selection circuitry making it all much simpler.

All of above can be made just from NAND or NAND gates instead of concrete IC implementation. For that you need to use Karnaugh Maps and Boolean algebra.

It is a while I done something with raw gates as now is much easier cheaper faster to use MCU/FPGA for all of this so beware I could have miss something trivial (like negation gate somewhere)... anyway even then this should got the idea behind timers

BTW C++ representation of this is:

int cnt=0,D=?;
bool TA=0;
for (;;)
 {
 if (cnt==D) TA=1;
 cnt=(cnt+1)&15;
 }

[Edit1] the 4 channels version

This is based on the above text. There is also another option with less components that use 4 nibble RAM module instead of LATCH registers and decoder composing of single timer continuously looping through all channels by 4 x times CP multiplied clock (for example by XORing delayed CP signals).