I am making my first ASIC and I am having trouble understanding something.
I have an internal clock of 80MHz that appears on a pin of the ASIC, the other pins include the data output pins connected to the D/A.
All the traces on this particular board will be of equal length and equal propagation delay, this includes the clock and the data pins, load capacitance for all the data pins is 5pf (each). The D/A has a 1 ns. setup time. The D/A is an output device only, there is no path back to the ASIC.
I calculated, based upon the trace length, width, thickness and proximity to the power planes on this board that it should take approximately 1 ns for an edge to travel from the ASIC to the D/A.
I proposed clocking the data to the pins on the negative edge of the clock and use the positive edge that appears on the ASIC pin to clock that data into the D/A.
The company I am working with says this is not enough time to guarantee clean arrivals and D/A output.
These people are professional and know what they are doing but I would like to get some understanding of what the difficulty is. Can someone point me to some reference material?
thank you.
As your data transmitted on negedge and sampled on posedge,
I proposed clocking the data to the pins on the negative edge of the clock and use the positive edge that appears on the ASIC pin to clock that data into the D/A.
Clock is of 80 MHz, so clock period be 12.5 nSec, but due to your specific implementation as quoted, you have only 6.25 nSec for usable time to compensate setup and propagation time, (1 nSec + 1 nSec = 2 nSec), so you have margin of 6.25 - 2 = 4.25 nSec.
It is completely fine, ask those people how they can say!