I am getting a different clock period, when I am simulating the Endian Swapper example of Cocotb in VHDL and Verilog mode using QuestaSim. The clock is generated in the same way for both modes in the provided example code:
@cocotb.coroutine
def clock_gen(signal):
while True:
signal <= 0
yield Timer(5000)
signal <= 1
yield Timer(5000)
@cocotb.coroutine
def run_test(dut): # stripped un
cocotb.fork(clock_gen(dut.clk))
When running in Verilog mode with:
make SIM=questa GUI=1
the clock period is 1000 ns (one thousand nano-seconds), and thus, the time resolution is 100 ps.
When running in VHDL mode with:
make SIM=questa GUI=1 TOPLEVEL_LANG=vhdl
the clock period is 10000 ns (ten thousand nano-seconds), and thus, the time resolution is 1 ns.
I am using the same clock generation in two other VHDL projects. In one I am getting a clock period of 10000 ns too, (1 ns resolution). But in the other one, the clock period is only 10 ns, giving a resolution of 1 ps.
Why differs the time resolution in all these run modes and projects?
How do I specifiy the time resolution consistently?
No time resolution is specified for the vsim command within the runsim.do file generated by the Makefiles. Thus, the default time resolution of the simulator is used as specified in the modelsim.ini. One of the other VHDL projects had a private modelsim.ini with a time resolution set to 1 ps (Resolution = ps) instead of the default 1 ns (Resolution = ns).
Additional vsim arguments can be specified by the Makefile variable VSIM_ARGS of the Cocotb build system. But setting this variable on the command line with:
make SIM=questa GUI=1 "VSIM_ARGS=-t 1ps"
does not work as expected because other required vsim arguments have now been stripped of.
One has to set this variable in the project-specific Makefile instead, e.g., just before including the system-wide Makefiles:
VSIM_ARGS=-t 1ps
include $(COCOTB)/makefiles/Makefile.inc
include $(COCOTB)/makefiles/Makefile.sim
This way, one gets a consistent time resolution across VHDL and Verilog. The parameter has to be set for every project accordingly.