vhdlprimeskarnaugh-map

Prime number detector between 0 and 101, digital logic karnaugh map

For the input of 101, one needs to have 7 bits, but I dunno how to start drawing a k-map with 7 variables...

Here's a tutorial on doing 5 variable k-map, and the SOP equation is:

F = a' b' e + a' b' c' d + b c d' e + a c d e + b' c' e + a' c' d e

Which I guess can be used in VHDL, you input some number, and F will output 1 if the number is prime (e.g. 7) or 0 if it's not. But this equation only supports number up to 31, how do I find an equation that'll cover prime numbers between 0 and 101??

How would I start doing the k-map? Would my a input also be separate kind of like the in the youtube example?

Solution

  • Follow the steps:

    1. Make truth table for 0 to 101, in which F should be 1 for prime number.
    2. Insert that truth table here.
    3. Obtain reduced boolean equation and Rock!!

    For more than six variable, It is too much tedious to handle K-Map Squares as it is too much. You can use Tabulation Method (Quine-McCluskey). See link.