low power circuit design in verilog and calculate power for different input sequences
I want to implement the following circuit in verilog. FA is the full adder circuit and trapezoidal shape is a mux. I am not sure how to add this power gating pmos in the circuit. And also I would like to synthesize the circuit in Synopsys Design vision and compute the difference in power when APP is 0 and 1.
Any help is appriciated.
Thanks
Farhana
Design two versions of the original circuit: one of them will assume the power switch is ON and the FA is operating. The other one will assume the power switch is OFF and then, the FA will be missing from the circuit. Leave the remaining devices (eg. muxes) on both circuits and set APP acoordingly.
Tell Synopsys to not perform any optimizations (it would remove the muxes as the select input is fixed to a certain value, but if it does so, the current compsumtion of the muxes, although neligible, wouldn´t be taken into account).
Perform a power analysis on both versions and you will get the difference in power.
The result you obtain will have to assume that the leakage current through the PMOS device is 0 when OFF
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