hardwarebootbiospcipci-bus

How is PCI ROM shadowed?


in several resources I found that: ROM image must be copied to RAM to 000C0000h through 000DFFFFh. If the Class Code indicates that this is the VGA device ROM, its code must be copied into memory starting at location 000C0000h.

1: What if I have PCI hungry hungry hippo card that has ROM bigger than 128KB?

2: What if I have regular PCI device that has ROM 64KB but I have 4 of them? Are they loaded sequentially into this memory range? If so (though I doubt that) how is the code image preserved between init and boot phase?

3: What would happen if BIOS decided to go nonconformist and designated a different memory location? Why is it important to use this range anyway?

4: how the hell is regular case different from VGA interface? Is it just the limit that makes the difference?


Solution

  • 1: It is not possible to have ROM this big copied into option ROM space. Init size field is 1 byte and it is interpreted as 512 byte increments, that's 255 * 512 = 127KB

    2: Too bad, some of them won't be initialized.

    3: There are PAMs in the northbridge(intel chipset datasheet). These registers can write protected specific ranges in optional ROM space.

    4: Limit counts for VGA too. It just has to start at c0000h, while some NIC can start at.. pfft d0000h as well.

    Thank you Pyjong. You are welcome Pyjong.