Verilog - Error: "Unresolved reference" when simulating

Using ModelSim. I'm trying to simulate an up-down two-bit counter. It compiles fine, but when I try to run the simulation, I get the following error:

** Error: (vsim-3043) D:/ModelSim/examples/Lab7.v(46): Unresolved reference to 'state'.

Module is:

module TwoBitCounter(input Dir, clock, reset);

reg[1:0] state;

parameter S0 = 2'b00, S1=2'b01, S2=2'b10, S3 = 2'b11;

always @(posedge clock or negedge reset)
    if (reset == 0) state<=S0;

    else case(state)
        S0: if(Dir) state = S1; else state = S3;
        S1: if(Dir) state = S2; else state = S0;
        S2: if(Dir) state = S3; else state = S1;
        S3: if(Dir) state = S0; else state = S2;
    endcase

endmodule

Testbench is:

module Counter_TB;

reg Dir, clock, reset;


TwoBitCounter DA0(.Dir(Dir), .clock(clock), .reset(reset) );

initial begin

reset = 0;
Dir = 1;

#5 reset = 1;

forever #205 Dir = ~Dir;

end

initial begin
clock = 0;
forever #25 clock = ~clock;
end



initial #800 $stop;

initial $monitor ("State AB: %b", state);

endmodule

Since state is an internal variable to the TwoBitCounter module, you get an error when you try to access it directly in the testbench module in the $monitor statement. You can access it with a hierarchical specifier:

initial $monitor(DA0.state);

Or, you can declare state as an output port of the TwoBitCounter module and connect to it in the testbench.