raspberry-pihdmiprojector

Split HDMI Image to 3D Projector System

I am quite stuck on a board, or something that could fit my needs.

I made a dual Projector 3D System at home, like this : http://www.cinema3dglass.com/Dual_projector_3D_polarization_system.php

And the HDMI can have different (8) formats(Left Right, Above Below, ect..) all here: https://www.tridef.com/user-guide/3d-file-formats

So the needed images on the incoming HDMI port can ble placed like above, and I need to split them on two separate HDMI outputs according to the format, so I can plug them into the projectors.
Basically I need a device that is in the first image in the first link above title: "HDMI Distribution Amplifier & EDID Emulator"

I know an Arduino can't handle this amount of processing, because I overloaded it with simlier tasks.
Can anyone Help me where to start? I foud Panda development board but that's too expensive.
Or if there is a not owerly expensive device existing for this task, I could buy that.
I manadged to use the system from Tridef 3D but that's hard to get working.

I'd like my device to get the input from a Chromecast 2.0, but if it's not possible a normal player 'll do it.

I found some devices called HDMI Demultiplexer they simply cut one half of the input, but that's quite expensieve, for 260$ and two would be needed.
Help me please.

Thanks in advance.

Solution

  • From the HDMI specification at page 56 the transfer/interconnection looks like this:

    HDMI

    I would start with interleaved left/right format where even pixels are left and odd pixels are right because there is high chance that it does not need any FIFO. If you want standard left/right then you need single line FIFO for each channel and for up/down full image FIFO. In case variable clock is supported by your HW then this simplified example should work:

    no FIFOs

    You need to add H/V sync decoder from Channel0 to reset the binary counter. Binary counter counts which data address is being processed. The single data-line to the AND gates should be D1 half of the input clock but not entirely you need to toggle between D0 and D1 depends in the timing of data processed (for pixels it would be D1 and for other data it would be D0) that is the variable clock I mentioned before. The comparator just compares the address against predefined constants (like half of line for non interleaved left/right format or detect even odd for interleaved format but both must take +/- other data offsets) beware the transfer is on bits not Bytes so the address will be multiplied by number of bits per data chunk ... The gates just toggle clock between left and right part. LATCHES make sure output signal will be not mixed and also boost the signal.

    I would start with oscilloscope measurements of the channels so you can see how the data is transfered and then experiment-ate. If you use FPGA then you do not need to make any changes to the board while ecxperimentating with configurations as the circuit will be solely inside FPGA.

    If variable clock is not supported then you need to use FIFO and or RAM to store the full line/image and then send the appropriate parts to their connectors. For that you most likely need full decoding capability so use the SIL9134 + SIL9135. Halving resolution will introduce timing problems because you will need more time to send half speed half frame then the full speed full frame (the auxiliary and sync data is copied not halved). If the sending has big enough gaps you could fit the missing time there but again not all HW can support it losing sync/flickering/etc. In such case you could change the resolution to a bit smaller (after halving) to fit in the send time ... or enlarge thi full resolution input (in x axis).

    Good luck with your quest.