I have the following Makefile:
CC=g++
top_srcdir=$(SRC_DIR)/cpp/src/
INCLUDES:= -I $(top_srcdir) -I $(top_srcdir)command_classes -I $(top_srcdir)platform -I $(top_srcdir)value_classes
LIBS:= -lopenzwave -lpthread -ludev
LDFLAGS += -L$(SRC_DIR) -Wl,-R$(SRC_DIR) '-Wl,-R$$ORIGIN'
all: ozw
ozw: Main.cpp
$(CC) $(INCLUDES) -c Main.cpp -o ozw-power-on-off.o
$(CC) $(LIBS) $(LDFLAGS) ozw-power-on-off.o -o ozw-power-on-off.out
clean:
rm -rf *.o *.out
I execute it with the following command:
make ARCH=$TARGET_ARCH \
CROSS_COMPILE=$TARGET_PREFIX \
SRC_DIR=$ROOT/$PKG_BUILD
But it ignores the ARCH
and CROSS_COMPILE
values. I tried to replace $(CC)
with $(MAKE)
and added -$(MAKEFLAGS)
, but it was saying Nothing to be done for 'Main.cpp'
.
How can I fix it and add cross compilation support?
A possible example of something I would try is below, assuming $ARCH gets mapped to "arm" in this trivial example. I haven't tested it, but I have done something similar before.
CC=g++
CC-arm=arm-g++
ozw: Main.cpp
$(CC-$(ARCH)) $(INCLUDES) -c Main.cpp -o ozw-power-on-off.o
$(CC-$(ARCH)) $(LIBS) $(LDFLAGS) ozw-power-on-off.o -o ozw-power-on-off.out
This assumes that the toolchain exists in your path.
It might also modify it such that CC=$(PREFIX)-g++
. It all depends on what you pass into it maps against your toolchain's naming convention.