Given a pipelined CPU, when and how does the CPU get interrupted by an interrupt or exception when executing instructions in a pipeline?
In what phase is the interrupt/exception handled, and what happens to the current pipeline and/or instruction on which the interrupt/fault occured?
It is very specific to the design of that processor and I dont just mean arm does this and x86 does that, it could be at that level but as each new core comes out, the designers may change how they do it.
The general programmers assumption is that it "finishes the current instruction" then interrupts, but if you look at the ARM ldm/stm at least some of them say they abort even if they have started, so dont use those instructions against logic that responds to reads or writes (never autoincrement for example), x86 for many years has said never to do that once branch prediction was added as the branch predictor can literally read anything just in case, so dont react other than to return a value.
With a pipe your question is no different than what happens when I branch/jump. Well perhaps it varies per instruction type, or perhaps it is generic, but obviously the pipe is interrupted, the things queued up in the pipe are discarded the interrupt routine is fetched/called and that coded executes, the return causes the processor to return to the instruction after the last one completely executed. It is basically no differen than a branch, you have to complete an instruction, stop and flush the pipe start executing somewhere else, the ret is like a branch you stop and flush the pipe and start back somewhere else. closer to a call/branch link than a simple branch but you get the idea I hope.
There is no magic here, nothing special, just think about a function call.
As to exactly where in the pipe, well there are hundreds to thousands of different pipelined processor designs, and there is no reason to expect any two of them to be the same so if that is the question then it is too broad, there is no one answer.