data bus and addressing memory confusion

I have learned 8086 CPU has 16bit data bus, and Pentium CPU has 32bit data bus, which mean each memory address holds size of data bus.

For example:

16bit = 2^16 = 65,536 
binary 0000 0000 0000 0000 ~ 1111 1111 1111 1111
hex    0000 0000 ~ FFFF FFFF
dec    000,000 ~ 65,535

65,536 / 1024 = 64 so can be 64kbyte of maximum memory address.
like 0x 0000,0000 ~ 0x FFFF,FFFF  


32bit = 2^32 = 4,294,967,296
binary 0000 0000 0000 0000 0000 0000 0000 0000 
~ 1111 1111 1111 1111 1111 1111 1111 1111
hex    0000 0000 0000 0000 ~ FFFF FFFF FFFF FFFF
dec    0,000,000,000 ~ 4,294,967,296

4,294,967,296 / 1024 / 1024 = 4 so can be 4mb of maximum memory address 
like 0x 0000,0000,0000,0000 ~ 0x FFFF,FFFF,FFFF,FFFF

Am I correct? I think so. But in C programming:

int arr[2];
printf("%p %p \n", &arr[0],&arr[1]);
-----------------------------------
0x 7fff5c474b20,  0x 7fff5c474b24  (this is 64bit addressing)

I know integer is 4 byte. Size of &arr[1]-&arr[0] is 0x4 which means every address holds only 8bit data bus.

If the CPU can hold more than 8bit why does C hold only 8bit?

Solution

Oups... Things are not exactly what you have written - I speak about the 8086 (I'm old enough to have worked with it...). You will find more references on it on wikipedia)

the data bus is 16 bits wide, meaning that is can transfer 2 bytes in one single operations
the address but is 20 bits wide, meaning that the memory addresses are in range 0 - 0xFFFFF or 1M

The 8086 used based addressing mode: an address was represented by a segment (16 bits register) and an offset, the actual address being segment * 16 + offset - btw, addresses had different representation for example 0x20010 could be represented as 2000:0010 or 2001:0000 1FFF:0020

And... there was no 64 bits addressing mode on a 8086!

Now for your actual question, C specifies that the smallest addressable memory shall be a char or byte, and that a single char shall contain any character from the alphabet used is C source (upper and lower case letters, digits, and some symbols so at least 7 bits). Common processors (all I know) use 8 bits byte addressing, independently of the bus size. That means that consecutive addresses are addresses of consecutive bytes.

The fact that be data bus is 16, 32 or 64 bits wide simply allow one single memory access to load respectively 2, 4 or 8 bytes on a single operation. Some processors (ARM for example) require multi-bytes memory accesses to be correctly aligned : you can read a 16 bit word only on even addresses for example and any attempt to read a 16 bits work from an odd address will result in a processor trap.

And remember that nothing (except simplicity) forces processor designer to have a data bus and an address bus of same size.