I am trying to test all possible cases of inputs for my Verilog code. I set it up with for loops.
for(sel = 0;sel < 4;sel=sel+1) begin
for(a = 0;a < 8;a=a+1) begin
for(b = 0;b < 8;b=b+1) begin
#50;
end
end
end
It was working earlier, but I must have changed something or Isim might have a bug. I initialized a, b and sel, too.
reg [2:0] a;
reg [2:0] b;
reg [1:0] sel;
When I try to simulate the tb file, it only loops through b repeatedly! Why could this be?
Also, when I change b bounds to <7, it will begin to loop through a, but I have to change a bounds to <7 to loop through sel. Although this partially works, it skips the cases of 111 for a and b and 11 for sel.
Furthermore, I decided to test the bits manually for all cases, and it's showing the correct result.
You have an infinite loop because your end condition (b < 8) is always true. You can easily prove this to yourself with the following code. You can see 0-7 repeating many times:
module tb;
reg [2:0] b;
initial begin
for (b = 0;b < 8;b=b+1) begin
$display(b);
#50;
end
end
initial #1000 $finish;
endmodule
Output:
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
Since you declared b as a 3-bit signal, it's range of values is 0 through 7. Therefore, b is always less than 8. When b=7, b+1=0, not 8.
Changing 8 to 7 displays only 0-6 once because the end condition (b < 7) becomes false.
Here is one way to loop from 0 to 7 once:
module tb;
reg [2:0] b;
initial begin
b = 0;
repeat (8) begin
$display(b);
#50;
b=b+1;
end
end
endmodule
Another common way is to declare b as an integer instead of a 3-bit reg. Then for (b = 0;b < 8;b=b+1) begin loops 0-7 once because b can increase to 8. An integer is a 32-bit signed value (refer to IEEE Std 1800-2012, section 6.11 Integer data types).