inputinterfacevhdlvirtex

how to connect LVDS signals coming from test equipment to fpga virtex 5 when the design has only input signal Din ?

I would provide din+ to A1 and din- to A2, on pin connector on PM2 module, connecting to FPGA, but I have only 1 input port "din" in top level vhdl design module connected to AG7 pin on FPGA. How to go about connection in UCF file ? 

PM2 Pin - A1, A2
FPGA pin -AG7, AG6 
FPGA bank VCCO - 2.5v, 2.5v
Pin Function - LVDS pair 100 ohm differential impedance; can also be used as single-ended
Solution

  • You have to manually instantiate the differential input buffer. For Xilinx it will be IBUFDS in the Unisim library. Either modify your port to have two pins for din and add the buffer in the existing design or write a simple wrapper that converts the diff. pairs to single-ended and pass that into the current port.