system-verilogsynopsys-vcs

SystemVerilog over vcs saving simulation state and rewinding

I am running a testbench using systemverilog over OVM using vcs. I want to save my simulation after some reset phase and then return to it later on in the test, or/and from another testbench. Is this possible using systemverilog cmds?

Alternatively is there a way to do this using vcs cmds? Thanks

Solution

  • Yes there is $save command in vcs, to save the session. That command needs to be placed in the design itself.

    In your case you can do something like this. 

    initial
begin
      reset = 1'b1; // Asserting Reset
  #10 reset = 1'b0; // Deasserting Reset
      $save ("reset_state.chk");
  //  Post reset data
end

    This will save the reset state in reset_state.chk file.