[SOLVED] In systemverilog is there a way to condition on a type?

In systemverilog is there a way to condition on a type?

So I am using a parameterized type in a common module.

Is there a way to say: if( type == TYPE1 ) assign the struct one way else if( type == TYPE2 ) assign another way

I was picturing this in a generate block.

Solution

Yes, you can use the type operator do a generate-if/case, or procedural if/case like:

real r;

if ( type(r) == type(real) ) ...

But unfortunately the code in all branches still must successfully compile, regardless of the condition. You will not be able to reference struct member that does not exist.

  typedef struct {int a;} s1_t;
  typedef struct {int a;int b;} s2_t;
  s1_t s;
 initial
      #1 // procedural-if
    if (type(s) == type(s1_t))
      $display("%m s.a = %0d",s.a);
    else if (type(s) == type(s2_t))
      $display("%m s.b ==%0d",s.b); // this will not compile