mappingportvhdl

Port mapping only working in some entities


I thought I got this mapping thing figured out, but it appears I don't... So, I've got the code below that has top entity (circuito) which has control and datapath entities inside. When I synthesize the project, it gives out a bunch of warnings (0 errors) basically saying all the ports in datapath (input and output) are not connected ("[Synth 8-3331] design datapath has unconnected port res[31]" and so on for all ports) and in fact, it doesn't connects the ports in the design and even deletes datapath entity, keeping control entity in circuito (So no problem with control). The reset and clk ports are the same for both entities, but it doesn't map that port to datapath, only to control. Help me out guys, what's wrong? Tell me if you need any more code.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;

entity circuito is
  port (
    clk, reset: in std_logic;
    x, c0, c1, c2, c3, c4, c5, c6, c7 : in signed(6 downto 0);
    res : out signed(31 downto 0);
    done : out std_logic
    );
end circuito;

architecture Behavioral of circuito is
  component control
    port(
     clk, reset, done : in std_logic;
     e_in : out std_logic;
     e_out : out std_logic;
     e_inter : out std_logic_vector (4 downto 0);
      mux_sel1, mux_sel2, mux_sel3, mux_sel5,  mux_sel6  : out std_logic_vector (1 downto 0);
     mux_sel4, mux_sel7 : out std_logic );
  end component;
    component datapath
    port(
         x, c0, c1, c2, c3, c4, c5, c6, c7 : in signed(6 downto 0);
              clk, reset : in std_logic;
              e_in : in std_logic;
              e_out : in std_logic;
              e_inter : in std_logic_vector (4 downto 0);
              mux_sel1, mux_sel2, mux_sel3, mux_sel5,  mux_sel6  : in std_logic_vector (1 downto 0);
              mux_sel4, mux_sel7 : in std_logic;
              res : out signed (31 downto 0);
              done : out std_logic );
  end component;

  signal e_in : std_logic;
  signal e_inter : std_logic_vector(4 downto 0);
  signal finish, e_out : std_logic;
  signal mux_sel1, mux_sel2, mux_sel3, mux_sel5, mux_sel6 : std_logic_vector (1 downto 0);
  signal mux_sel4, mux_sel7 : std_logic;

begin

inst_datapath: datapath port map(
    clk => clk,
    reset => reset,
    done => finish,
    e_in => e_in,
    e_out => e_out,
    e_inter => e_inter,
    mux_sel1 => mux_sel1,
    mux_sel2 => mux_sel2,
    mux_sel3 => mux_sel3,
    mux_sel4 => mux_sel4,
    mux_sel5 => mux_sel5,
    mux_sel6 => mux_sel6,
    mux_sel7 => mux_sel7,
    res => res,
    x => x,
   c0 => c0,
   c1 => c1,
   c2 => c2,
   c3 => c3,
   c4 => c4,
   c5 => c5,
   c6 => c6,
   c7 => c7
   );
inst_control: control port map(
    clk => clk,
    reset => reset,
    done => finish,
    e_in => e_in,
    e_out => e_out,
    e_inter => e_inter,
    mux_sel1 => mux_sel1,
    mux_sel2 => mux_sel2,
    mux_sel3 => mux_sel3,
    mux_sel4 => mux_sel4,
    mux_sel5 => mux_sel5,
    mux_sel6 => mux_sel6,
    mux_sel7 => mux_sel7
    );    

end Behavioral;

Where datapath component is implemented with:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;


--Datapath entity
entity datapath is
    port ( x, c0, c1, c2, c3, c4, c5, c6, c7 : in signed(6 downto 0);
           clk, reset : in std_logic;
           e_in : in std_logic;
           e_out : in std_logic;
           e_inter : in std_logic_vector (4 downto 0);
           mux_sel1, mux_sel2, mux_sel3, mux_sel5,  mux_sel6  : in std_logic_vector (1 downto 0);
           mux_sel4, mux_sel7 : in std_logic;
           res : out signed (31 downto 0);
           done : out std_logic       
           );
end datapath;

architecture Behavioral of datapath is
    signal Rx, Rc0, Rc1, Rc2, Rc3, Rc4, Rc5, Rc6, Rc7 : signed(6 downto 0) := (others => '0');
    signal Rout : signed(31 downto 0) := (others => '0');
    signal R1, R2, R3, R4, Rx2 : signed(31 downto 0) := (others => '0');
    signal add1, add2, mul1, mul2 : signed(31 downto 0) := (others => '0');
    signal mux1, mux2, mux3, mux4, mux5, mux6, mux7 : signed(31 downto 0) := (others => '0');
    
begin
--"Fixed" Input Registers:

--Register Rc0
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                Rc0 <= "0000000";
            elsif e_in = '1'then
                Rc0 <= c0;
            end if;
        end if;
    end process;

--Register Rc1
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                Rc1 <= "0000000";
            elsif e_in = '1'then
                Rc1 <= c1;
            end if;
        end if;
    end process;

--Register Rc2
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                Rc2 <= "0000000";
            elsif e_in = '1'then
                Rc2 <= c2;
            end if;
        end if;
    end process;

--Register Rc3
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                Rc3 <= "0000000";
            elsif e_in = '1'then
                Rc3 <= c3;
            end if;
        end if;
    end process;
    
--Register Rc4
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                Rc4 <= "0000000";
            elsif e_in = '1'then
                Rc4 <= c4;
            end if;
        end if;
    end process;
    
--Register Rc5
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                Rc5 <= "0000000";
            elsif e_in = '1'then
                Rc5 <= c5;
            end if;
        end if;
    end process;
    
--Register Rc6
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                Rc6 <= "0000000";
            elsif e_in = '1'then
                Rc6 <= c6;
            end if;
        end if;
    end process;
    
--Register Rc7
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                Rc7 <= "0000000";
            elsif e_in = '1'then
                Rc7 <= c7;
            end if;
        end if;
    end process;
    
--Register Rx
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                Rx <= "0000000";
            elsif e_in = '1'then
                Rx <= x;
            end if;
        end if;
    end process;

--Intermediate Registers:

    --Register R1
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                R1 <= X"00000000";
            elsif e_inter(0) = '1'then
                R1 <= mul1;
            end if;
        end if;
    end process;
    
    --Register R2
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                R2 <= X"00000000";
            elsif e_inter(1) = '1'then
                R2 <= mul2;
            end if;
        end if;
    end process;
        
    --Register R3
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                R3 <= X"00000000";
            elsif e_inter(2) = '1'then
                R3 <= add1;
            end if;
        end if;
    end process;
    
    --Register R4
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                R4 <= X"00000000";
            elsif e_inter(3) = '1'then
                R4 <= add2;
            end if;
        end if;
    end process;
    
    --Register Rx2
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                Rx2 <= X"00000000";
            elsif e_inter(4) = '1'then
                Rx2 <= mul1;
            end if;
        end if;
    end process;
    
    --Multiplexer1
    mux1 <= resize(Rc7, mux1'length) when mux_sel1 = B"00" else
            resize(Rx, mux1'length) when mux_sel1 = B"01" else
            resize(R3, mux1'length) when mux_sel1 = B"10" else
            resize(Rx2, mux1'length) ;
            
    --Multiplexer2
    mux2 <= resize(Rx, mux2'length) when mux_sel2 = B"00" else
            resize(Rx2, mux2'length) when mux_sel2 = B"01" else
            resize(R1, mux2'length) ;
            
    --Multiplexer3
    mux3 <= resize(Rc7, mux3'length) when mux_sel3 = B"00" else
            resize(Rc3, mux3'length) when mux_sel3 = B"01" else
            resize(Rc1, mux3'length) when mux_sel3 = B"10" else
            resize(R3, mux3'length) ;
            
    --Multiplexer4
    mux4 <= resize(Rx, mux4'length) when mux_sel4 = '0' else
            resize(Rx2, mux4'length) when mux_sel4 = '1';
    
    --Multiplexer5
    mux5 <= resize(R1, mux5'length) when mux_sel5 = B"00" else
            resize(Rc2, mux5'length) when mux_sel5 = B"01" else
            resize(R4, mux5'length) when mux_sel5 = B"10" else
            resize(R3, mux5'length) ;
            
    --Multiplexer6
    mux6 <= resize(Rc6, mux6'length) when mux_sel6 = B"00" else
            resize(R2, mux6'length) when mux_sel6 = B"01" else
            resize(Rx2, mux6'length);
            
    --Multiplexer7
    mux7 <= resize(Rc4, mux7'length) when mux_sel7 = '0' else
            resize(Rc0, mux7'length) when mux_sel7 = '1';
            
    
    --Adder1
    add1 <= resize(mux5 + mux6, add1'length) ;
        
    --Adder2
    add2 <= resize(R2 + mux7, add1'length) ;
        
    --Multiplier1
    mul1 <= resize(mux1 * mux2, mul1'length) ;
        
    --Multiplier1
    mul2 <= resize(mux3 * mux4, mul2'length) ;
    
    
    --"Fixed" Output Register:
    
    --Register Rout
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                Rout <= X"00000000";
            elsif (e_out = '1') then
                Rout <= R3;
                done <= '1';
            end if;
        end if;
    end process;
    
    res <= Rout;

end Behavioral;

EDIT: Made some changes, no idea what worked, but now only have c5 port unconnected, both in circuito and datapath


Solution

  • From the comments, the output e_inter of control is always all zeroes. Following this through to your error, the signal res in datapath is assigned thus:

    if clk'event and clk = '1'then
        if reset = '1' then
            Rout <= X"00000000";
        elsif (e_out = '1') then
            Rout <= R3;
            done <= '1';
        end if;
    end if;
    

    ...

    res <= Rout;
    

    R3 is driven thus:

    if clk'event and clk = '1'then
        if reset = '1' then
            R3 <= X"00000000";
        elsif e_inter(2) = '1'then
            R3 <= add1;
        end if;
    end if;
    

    From these two code snippets, we can see that if e_inter(2) is always '0', the only assignment that can be made to res is to reset it to all zeroes. Since this port is therefore a constant, the tools will optimise it away.

    The basic method for diagnosing this kind of issue is to look at the warnings. There can often be a lot of useless warnings, which can make this process tedious, but you should be able to use message filtering to thin them out a bit, revealing useful messages. In this case, there should have been messages telling you that logic and/or signals were being removed due to constants propagation or simmilar.