I'm working on a project about the Mali 450 GPU. In the diagram I noticed that there is only a level 2 cache which doesn't make sense based on what I have learned in class. From what I understand, the level 1 cache is always the closest and smallest cache, and so this should be labeled the level 1 cache. Or is there a level 1 cache that isn't labeled on the diagram?
Also, as a side question for clarification: Would the level 2 cache be responsible for storing image/video data that could be used/referenced again?
The level 1 caches are often not drawn on diagrams such as these because they are integrated within each vertex/fragment processor, whereas the level 2 caches are typically shared between several vertex/fragment processors.
Would the level 2 cache be responsible for storing image/video data that could be used/referenced again?
Yes; any data that is likely to be used/referenced again.
