makefile always calling the last target

This is my makefile.

#starts here
#Openssl constants
Openssl_include=-I/usr/local/openssl/include
Openssl_lib=-L/usr/local/openssl/lib -lcrypto -ldl
#Wolfssl constants
Wolfssl_include=-I/usr/local/wolfssl/include -LLIBDIR -DWOLFSSL_SHA512
Wolfssl_lib=-L/usr/local/wolfssl/lib -lwolfssl
#Mbedssl constants 
Mbedssl_include=-I/usr/local/mbedssl/include
Mbedssl_lib=-L/usr/local/mbedssl/lib -lmbedcrypto

SRC=CAL_aes.c CAL_sha.c CAL_cmac.c CAL_rsa.c
OBJ=$(patsubst %.c,%.o,$(SRC))
M_OBJ=$(patsubst %.c,M_%.o,$(SRC))
M_fpic_OBJ=$(patsubst %.c,M_fpic_%.o,$(SRC))

O_OBJ=$(patsubst %.c,O_%.o,$(SRC))
O_fpic_OBJ=$(patsubst %.c,O_fpic_%.o,$(SRC))

W_OBJ=$(patsubst %.c,W_%.o,$(SRC))
W_fpic_OBJ=$(patsubst %.c,W_fpic_%.o,$(SRC))

.PHONY: clean Openssl Wolfssl Mbedssl compile_openssl compile_wolfssl compile_mbedssl
compile_openssl: $(OBJ)  
%.o: %.c
    cc -c $^ -o $(patsubst $@,O_$@,$@) $(Openssl_include) $(Openssl_lib)
    cc -c -fpic $^ -o $(patsubst $@,O_fpic_$@,$@) $(Openssl_include) $(Openssl_lib)
Openssl: compile_openssl
    ar rc libO_CAL_crypto.a $(O_OBJ)
    cc -shared -o libO_CAL_crypto.so $(O_fpic_OBJ)
compile_wolfssl: $(OBJ)  
%.o: %.c
   cc -c $^ -o $(patsubst $@,W_$@,$@) $(Wolfssl_include) $(Wolfssl_lib)
   cc -c -fpic $^ -o $(patsubst $@,W_fpic_$@,$@) $(Wolfssl_include) $(Wolfssl_lib)
Wolfssl: compile_wolfssl
        ar rc libW_CAL_crypto.a $(W_OBJ)
        cc -shared -o libW_CAL_crypto.so $(W_fpic_OBJ)
compile_mbedssl: $(OBJ)  
    %.o: %.c
        cc -c $^ -o $(patsubst $@,M_$@,$@) $(Mbedssl_include) $(Mbedssl_lib)
        cc -c -fpic $^ -o $(patsubst $@,M_fpic_$@,$@) $(Mbedssl_include) $(Mbedssl_lib)
Mbedssl: compile_mbedssl
        ar rc libM_CAL_crypto.a $(M_OBJ)
        cc -shared -o libM_CAL_crypto.so $(M_fpic_OBJ)
    #ends here

Irrespective of whether I make a call to Make Openssl , Make Wolfssl or Make Mbedssl. Always the target Make Mbedssl is getting called. I tried rearranging the targets, and all the time the target in the last position is getting called irrespective of the target that I passed to make from the command line. Thanks.

Solution

You seem to be trying to declare multiple instances of the pattern rule %.o : %.c so they'll have different affects depending on where they appear in the makefile. That's not possible. Make reads the entire makefile first, before it starts to process any targets, and it has only one "scope" for all rules.

If you redefine the pattern rule %.o : %.c then the old rule is deleted and the new rule takes effect for all lookups.

So the last instance of the %.o : %.c pattern is the one that is in effect for all lookups of .o targets, and all previous rules are deleted.

I recommend that you look into target-specific variables which might help you with the implementation.