cachingmemorycpu-architecturememory-addresswrite-through

Memory access frequency in write through cache (write allocate/ No write allocate)?


I'm little bit confused for memory accesses in case of write through cache for both write allocate and no write allocate.

Suppose we've a cache with line size of 4 word. How much words will be transferred between cache and memory in case of cache hi and miss if:

Thanks...


Solution

  • I think its implementation dependent.

    Lets consider no-write allocate and a cache write HIT. Since its cache HIT, you dont need to fetch from memory, However since its a write through, you DO need to update the main memory. If your architecture supports masked writes, i.e, it can send the address at 4 word granularity and a mask of actual dirty word, then you can get away with only sending a word. So on the memory's end, when it receives the write through request, it should be able to only update the word that is being modified, based on the mask and the address. In case of cache write MISS, since its no-write allocate, you dont need to fetch anything. You still need to update the main memory, again the same as above.

    When you consider the Write allocate, when it is a HIT, behavior is similar to above. When its a miss, you need to fetch the entry before modifying. Normally this is implemented similar to a read miss. So you'd fetch 4 words, and the rest is the same for writing back to memory.

    So the bottomline, fetching from memory will always be 4 words. Writing to memory will be 1 word or 4 words, depending on the implementation.