If the period of the system clock is T then how can we delay the clock by 1/4 T without using any analog device? A synthesizable VHDL code is preferred.
You cannot delay by any fraction of a clock period reliably using digital electronics. (Whether you code it in VHDL or Verilog or Palasm or Ella or whatever is irrelevant.)
You can delay a clock by roughly 1/2T if you use the opposite edge of the clock, but even this is not reliable. In doing so you are assuming that the mark-space ratio of the clock is close to 50:50 and that will be the case whatever the supply voltage, die temperature (temperature of the actual silicon) or process corner (speed grade of the FPGA).
The only way you can delay by less than 1/2T is to exploit the fact that any logic gate has a delay through it. However, this is a very unreliable method, because that delay will vary considerably with supply voltage, die temperature and process corner. For example easily by a factor of 3.
So, if you want to delay something by 1/4T reliably, you need a clock with period 1/4T.