On ISE 14.7, what do I need to do in order to have the AXI stream (which has an ipcore that loops a value) to give me output via the UART?
I had set up the project properly, added a UART and set the mhs, ucf files and the rest of the bonanza, however I do not have any idea what do I need to do to have output from the AXI via the UART.
Any ideas?
You will need to write an UART module in RTL or use an existing Ip-core which accepts AXI-stream transaction and converts it to UART messages.
However due to performance differences it is more common to find IP-cores with AXI4-Lite interface to UART. For example AXI UART 16550 (https://www.xilinx.com/support/documentation/ip_documentation/axi_uart16550/v2_0/pg143-axi-uart16550.pdf)