If for a given process, I declare a variable (let's say a 1 bit variable, variable temp : std_logic;) then can I assign a value to the variable if a given condition returns true, i.e.
if (xyz=1) then --Assuming that this condition returns TRUE
temp:= '1';
?? Will this logic be synthesizable for ASICs?
Yes. Variables are synthesisable for both FPGA and IC. A process is a little bit of software that models a little bit of hardware. That little bit of software can use variables, but as variables are only in scope within a process, ultimately you do have to drive a signal - the output of the little bit of hardware.
For example, here is some combinational logic:
process (A, B, C, D)
variable TMP : std_logic;
begin
if A = '1' then
TMP := B and C;
TMP := TMP and D;
else
TMP := '0';
end if;
F <= TMP;
end process;
Here is an example of using a variable that will synthesise to combinational logic on the D input of a flip-flop (because it is in a clocked process):
process (CLOCK)
variable TMP : std_logic;
begin
if rising_edge(CLOCK) then
TMP := A and B;
Q <= TMP;
end if;
end process;
And here is an example of using a variable in a clocked process that will synthesise to a flip-flop (with an AND gate on its D input):
process (CLOCK)
variable TMP : std_logic;
begin
if rising_edge(CLOCK) then
Q <= TMP;
TMP := A and B;
end if;
end process;
The only difference between the two clocked processes is the order. In the first, the variable is assigned to before being accessed; in the second, it is accessed before it is assigned to.
If you assign to a variable before accessing it in a clocked process combinational logic will be inferred;
if you access a variable before assigning to it in a clocked process, a flip-flop will be inferred.
Do not ever access a variable before assigning to it in a combinational process: latches will be inferred.
Variables retain their value between executions of a process. Therefore, if a variable is accessed before being assigned to in a clocked process, the value read must have been written on a previous execution of the process. In a clocked process, that previous execution will have been on a previous clock edge: hence, a flip-flop is inferred.